The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device of the type of pipeline operation that is capable of operating at a high speed owing to the reduction in the cycle time.
It is widely accepted practice to provide a latch circuit in a semiconductor memory device. For instance, Japanese Patent Laid-Open No. 58-128097 discloses an art in which an address latch circuit is provided in the input portion (address buffer portion) of the address decoder and an output latch circuit is provided in the data output portion (output buffer portion). With the latch circuits being incorporated in the semiconductor memory device as described above, the memory circuit can be operated with a cycle time which is slightly greater than the delay time of a circuit between the latch circuits; i.e., the so-called pipeline operation can be effected to increase the operation speed of the memory circuit.
According to the above-mentioned prior art, however, an address decoder, a memory cell array unit and a sense circuit are inserted between the address latch circuit and the output latch circuit making it difficult to reduce the cycle time in the memory operation to be shorter than the sum of delay times of these three circuits.
Sense circuits in the memory devices have been disclosed, for example, in (1) "A 4K-bit Static I.sup.2 L Memory" (Kawarada et al.), IEEE Transactions on Electron Devices, Vol. ED-26, No. 6, June 1979, pp. 886-892, (2) Japanese Patent Laid-Open No. 53-39049, and (3) "A 12 ns/350 mW 16 Kb ECL Compatible RAM" (Okada et al.), ESSCIRC-85, Digest of Technical Papers, Sept., 1985, pp. 166-176.
Furthermore, a conventional semiconductor circuit used as an address decoder circuit in the memory device can be represented by a circuit of the type in which a wired OR gate based on the ECL gate and a NAND gate are combined together as a decoder circuit for the bipolar memory (e.g., see Japanese Utility Model Registration No. 1481216).
FIG. 1 illustrates a decoder circuit based on the ECL gate that has heretofore been used, containing three buffer circuits XB.sub.0, XB.sub.1, and XB.sub.2. The buffer circuit XB.sub.0 consists of two transistors Q.sub.1, Q.sub.2, two resistors R.sub.1, R.sub.2, a current source Is, and eight emitter followers EF.sub.1, . . . , EF.sub.8. The buffer circuits XB.sub.1 and XB.sub.2 have also been constituted in the same manner. Outputs of the emitter followers are suitable combined and partially decoded by means of wired OR. In the diagramed example, outputs of the buffer circuits XB.sub.0, XB.sub.1 and XB.sub.2 are partially decoded by wired OR in order to obtain eight partially decoded outputs X.sub.2 .multidot.X.sub.1 .multidot.X.sub.0, . . . , X.sub.2 .multidot.X.sub.1 .multidot.X.sub.0. These outputs are low when the input addresses are particularly combined. For example, the output X.sub.2 .multidot.X.sub.1 .multidot.X.sub.0 is low only when all inputs X.sub.0,X.sub.1 and X.sub.2 are high. In FIG. 1, the output X.sub.2 .multidot.X.sub.1 .multidot.X.sub.0 is connected to an input (base of the transistor Q.sub.C1) of the NAND gate GO.
In the above-mentioned conventional decoder circuit, the delay time increases with the increase in the number of wired OR's. By contrast when the number of the wired OR's is decreased the number of NAND inputs of the ECL gate increases for receiving the wired OR outputs, and thereby the time constant of the collector of the NAND gate increases causing the delay time to be increased. In practice, the device is designed finding a suitable compromising point between the two, which makes it difficult to accomplish the high-speed operation. Therefore, a transistor gate (see Japanese Patent Publication No. 60-20836) equipped with a pull-up circuit has been used as a high-speed decoder. In the decoder of this system, in general, the amplitude of the decoder line is determined by the amplitude of the word line, and is relatively large. Therefore, one of the effective method of operating the decoder of this type at high speeds is to decrease the amplitude of the decoder line. When the amplitude is decreased, however, the output level greatly varies depending upon the logical combination of the address inputs, making it difficult to accomplish high-speed operation. Furthermore, compared with the above-mentioned decoder of the type in which the wired OR and the ECL gate are combined together, the decoder of this type operates at a very high speed but requires complex circuit structure and is difficult to design. Moreover, it is difficult to decrease the width of the wiring for supplying large currents to the decoder lines, which imposes limitations on increasing the degree of integration.